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The next talk is
being held by Matthias Lazar,
Matthias is talking about how to reverse
engineer FPGA as
he did it by himself, and he will tell
you how he did it
and how he
especially reverse engineer the Killing
seven series and Lattice.
I see 40 series.
He knows much more about this than me, so
please give him a warm applause.
And here's Matthias.
I hello,
can you hear me OK?
Um, this.
What is this talk about in
this talk? I'm going to explain
to you what is an FPGA?
How does it work?
What does it do?
What does FPGA stand for?
And of course, I will tell you stories on
how I reverse engineered them.
Show you some pictures.
And so on.
What this story isn't about.
The talk is not about how to use
refugees.
I actually cannot use them.
I never learned very long of HDL
and its targets. It's not about high
level synthesis.
Maybe a quick story why I decided
to reverse engineer the I thought, the
series four years ago.
I wanted to build a small CPU
and at the problem that chip design
and building chips is far too expensive.
So the next simpler solution
would be an
FPGA.
But I did not want to learn very long
of all of it.
So I decided to sit down
and document the bitstream format
and the internal layout.
Anyhow.
FPGA stands for Field
programable Gate Array.
What means field programable,
in a sense, it means that the device
is in place programable,
so to say in life circuits,
we can just reconfigure the device.
The gate part is a FPGA
simulates or implements logic gates.
A.
Yeah, it's a two dimensional array of
logic gates, programable logic
gates.
Yes.
But what is logic
before I will tell you
how an FPGA works
and.
So far, we have to get down to.
Logic one on one.
We have four operators
are operators, yeah,
we have not gate with the
gate, with the arrogate and with the
exclusive brigade.
On the bottom, you can see the truth
tables when we have
the input, for example, at the augured
zero zero, we get zero on the output.
When we have zero one, we get one.
And so for.
Next thing we can.
Jane, to get a logic gates
into circuits.
Here is a small example of
one bit full error.
Which is used to implement additions.
And as you can see, it uses
two exclusive organs
to end gates up.
This one is a three expletive.
OK. The seven implementations of them.
In.
On the former slide,
we could see that we can generate
truth table dependent
on the input states.
And what we get on the output.
With that, we also can combine several
logic gates into
one table.
I did the work for the full letter
here.
And now.
We have our free inputs with two outputs.
And if we,
for example, get on a.
One on be zero.
And we have to carry that one.
We know the result will be zero and the
carry out will be one.
The nice part about this is we don't have
to trade through the logic and we
just kind of implemented
thorough logic gates in a lookup
table and the lookup
table is the smallest
part in the FPGA.
This thing implements the logic gates.
However.
We need more than one lookup table, of
course.
So let's zoom out a bit.
What you can see here
is a slice in these seven serious
sailings of a.
These are four lookup tables with
six inputs each.
They are followed by a special
care unit because
implementing addition with
lookup tables would take up too many
resources and because we need
it quite often,
it is far cheaper for the manufacturers
to include a carry chain.
And then on the outputs,
we have flip flops because
sometimes we need to synchronize the
state or we need to store
one bit of information.
We then pack together one lookup
table, one part of the carry chain,
and in case of the seven series two
flip flops into what's called
a logic cell.
For logic cells.
Make up one slice.
And two slices.
Our own group together.
Combined with a switch, books and
interconnect.
Into a tile.
As you can see, we have surrounding
tiles.
And that's how we implement logic,
and that's how we wired the logic.
Now we zoom out a bit more.
Yeah, we can see.
But several of those tiles are grouped
together into columns.
And we zoom out a bit more.
One column, which the seven series
contains 50 details
and one cocktail in the middle.
This is a rather small device.
It only has one hundred
eighty six columns.
Which equates to nine
thousand three hundred tiles.
The columns then are grouped together
into regions.
This particular device has six of them.
And yeah, that's
the basic fabric, but we're
still missing something.
We still can't communicate with the
outside world of the chip.
For something for that,
we need something like a bridge or
input output modules.
So at the borders, we have
the ayatollahs.
But are there more than
those two title types?
Of course, sometimes logic
is not enough.
Maybe we need memory.
Of course, we could implement the memory
and logic, but that's expensive to
sort of and gave us
small units called block room.
Here are two columns.
Locker room in that particular device.
Each small rectangle contains
36 kilobits of memory
and there are 140.
Yeah, blocks of RAM in this device.
Sometimes memories are not
enough.
Sometimes we need processing power.
Implementing arrhythmic
functions like multiplication
would also use up lots and lots of
resources, lots and lots of logic.
Sort of endorse gave us DSP
Tiles DSP
stands for digital signal processor
or in that case, it's just the small
addition units.
Combined with multiplication units.
OK, now we
really know about the basic makeup of
FPGA.
But how do we configure
it?
How does each lookup table knows
its values, how to
do to flip flops, know the initial state?
And how is everything relative?
For that, we have to bitstream.
Problem with the bitstream is it is
undocumented.
Yeah, and it's confused the switch box
is looked at, favors provides the initial
stage.
This thing decides which switch to turn
off and on.
The goal of reverse reverse engineering
effort is.
It's getting the bitstream documented.
Four years ago, I reverse engineered this
40th.
Quick summary
The 40 FPGA is
a very, very small one.
It is optimized for low power
consumption.
It only has between
three hundred eighty four and seven
thousand six hundred eighty lookup tables
with only four inputs.
Even the block room looks a small,
but is very beginners friendly, and
it's the cheapest one of Moussa.
This is the picture.
The manufacturer gives us.
It shows that programable
logic blocks.
Contain following
contain eight lookup tables.
And that the whole fabric is surrounded
with the ayatollahs.
But we don't know anything
about the interconnect,
and we don't even know how many
tiles, how many rolls and how many
columns there are.
A closer look at the control
of logic block order in that case,
the logic cell,
we can see there's only one flip
flop and it can
be bypassed.
You can use both the pure output
of the lookup table and the Flip-Flop,
and we only four inputs.
What's special about the rioting
in the eyes 40?
Is there are to be directional?
So you have more than one source
at each while you
can if you put in the right or
wrong configuration because short
circuits in the device itself.
Another thing they provide us with eight
globally relative signatures, they get
relative to every single tile and
every tile we can choose
out of those eight for.
The interconnect between
the tiles mainly consists
of wires that span over
four tiles and over 12 tiles horizontally
and vertically.
And, of course, everything tile is
connected with its surrounding neighbors.
That's it.
What were the challenges with
reverse engineering the 40 FPGA?
Well, we had no knowledge
about the internal layout.
I had no schematic.
I had no idea at all how many
wires there were.
Where to go, where to switch boxes are
power to switch boxes, connect
to the control of logic blocks,
and even the bitstream well
commands for
commanding the FPGA
to load correct bitstream were only
partially documented.
Another challenge, of course, is
mapping the Thai location to the bitmap
coordinates. But I will show you more
details of that later.
So how do they reverse engineer the
40 FPGA?
Well.
I took a look, took a closer
look at the towards
the vendors gave me.
Especially the bitstream generator,
the bitstream generator seemed to contain
several strings.
Which related to the names of the wiring
and you kept comparing the bit names,
but.
They were behind the debug flag
that I could not reach.
Because they commented it
out and a compiler didn't optimize adult.
That's why it was easy for me to document
and and reverse engineer this 40
FPGA because I only had
to replace one single Trump instruction
in the window tour.
And I was able to get every single name
of every single bit there was and
a short description of its function.
All right.
Not a fun story about how
this tool was written
when it tried to decompile it and
looked through some functions in it.
You could see where
the copy pasted everything together.
If you have one function and it's a
combination of print f's and see
out, you know.
They copy and paste that shit together.
Another thing I noticed
the bitstream contained
CRC or cyclic redundancy check.
But there was not a single
opcode that related to
this function, namely, excuse
me for the whole binary, had none.
If you implement the slightly redundancy
check you normally need it for.
That puzzles me.
So I just randomly stopped the
bitstream generator and took a look at
the memory dump, and they found
out they generated the bitstream
in ASCII.
So at some point I found it
in string of ones and
zeroes in asking.
And they generated that part only
for the CRC.
I don't know what happened in that
program.
I don't want to know what led to
these decisions, but
Wolf.
With the signing seven series,
I reverse engineered or partially
reverse engineer deciding seven series
two years ago.
I had another challenge because the
sailing series,
the seven series, it is really,
really high, a high performance device.
One thing looked at
six lookup table.
Uses up half the memory
of one small detail
in the eyes 40
and even the smallest seven years, FPGA
has my lookup tables that are far
bigger than the S40 ones.
And the biggest one has more than 1.2
million lookup table.
This maps to around 150000
tiles.
Yeah, a lot of resources in
the seventh year is.
Contain and block them,
the block arm has 36 killer bits of data,
as I mentioned before.
We have the central clock line.
The DSP calls the all times, by the way,
this is just the.
Bottom most part of the
sink seven to 20 later.
I will tell you more on that, I will tell
you more about the thing seven to 20.
This is the particular day it was decided
to reverse engineer.
Because it contained two
arm Cortex-A9 processor cores
that could reprogram the FPGA
and interface with it.
I really, really liked the fourth
about combining.
And FPGA with the
interconnect, with the memory system
of the processor cores and use that.
But then again, I didn't want to learn
very of HDL.
So I decided to reverse engineer it.
With the seven series,
I am.
I had to scale up my whole operations.
Because, for example,
as I mentioned before, then nine falls in
France, which boxes
each
switch books.
Contains.
Two hundred and sixteen multiplexes,
and they have three thousand seven
hundred thirty eight possible connection
states.
That's a lot.
They also connect through 135
words to neighboring tiles
and rolled 117 wires
from neighboring tiles to them.
The whole operation's suddenly got
very big.
And of course, the whole divide contains
more than three million wires, and
there are four to two
million or more than 32
million configuration split
with each of them.
I had to find out what they do.
What were the challenges with the seven
serious yet the complex design,
but with this one?
I was not able to get.
Any debugging information whatsoever?
Arthur, the Tudor chain, was much
more complex than the letters one.
It was first it was written in Java.
So, no, the compiling
there for me, I'm only
a C Assembly C++ programmer.
And it was written much nicer.
Another thing that bothered me, I will
show you shortly,
is that there is a small part
where the pattern of
the bitmap you can extract out of the
bitstream doesn't match.
The rest.
And this part is, as I later found
out, for the error correction part.
Also, not a small challenge,
also mapping the Thai locations
to the bitmap coordinates.
Now I will show you a very small
section of the bitmap.
You can I can generate of the
bitstream.
OK.
When I first looked at this,
I was like, fuck.
This thing seemed
like an insurmountable
wall to me, but
I already did.
And you already can see some patterns
in there.
We, for example, can see that there
are some bigger chunks,
most probably.
These are the configuration
data for the lookup tables.
Nice.
Now we only have to find out what
the other columns that look like
noise do.
Of course they are for the switch boxes,
but mapping them
to the to the sink wires.
I was hard.
About mapping the tiles
to the bitmap.
I have another picture.
We can see that 64
pixels mapped to one tile.
And this part.
Or, yeah,
this part.
Maps to the
other part.
With the middle part, I was puzzled.
Of course, the small,
regular flock of pixels we
can see here and here and
here had to have
had to do how to
how to.
Had to be used to forward the clock
interconnect with.
You're in the middle, we can see there's
the clock.
We know that 25 tiles on one
side and 25 tiles on the other side.
But that's all I got.
First to work with
about the ELO collecting court that we
can see there, if that thing was
a challenge, but I had an idea.
I wrote a small
parcel with counted the number
of bits that were set in each role.
If this number was
one, I
start the information about the
middle part.
Out of that, I was able to find out.
This thing was using Heming in court
or single conviction, purely error
detection, extend the timing called.
I would love to show you
more, but right
now I had a problem with
my hard disk and my notebook.
And that's kind of where my talk.
Early, and I think.
Hmm.
What can I tell you more about the
reverse engineering of the seven serious?
With the divided tour chain we get
in, at least we get the internal
schematic.
And you can extract it
automatically.
You get the informations on the
tile coordinates, you get the names of
the wires.
But we don't get the information in the
bitstream, but with the knowledge
of where the tile sits in the bitstream.
We can correlate that data.
I created several ultimate tools for
that. I would have loved to show
them to you, but
something went terribly wrong.
I'm sorry.
So what are the implications
of my work?
I did there.
Because I can
create a net list out of the bitstream,
I'm able to
cross compile bitstream different
architectures.
We've said we can copy extract and
reverse engineer IP course, but.
Are otherwise impenetrable.
Another possibility is starting
project as another project, I start
with Clifford together to create a
second target
for his open source tool chain.
I'm very sorry that my dog got
this short.
Yeah.
Any questions?
This was very short indeed.
So if you have questions
for Matt, please come to the microphones.
He is one to three
and four and
we have we can take questions from
the IOC at all via Twitter as
well.
Yeah, we have a question here at
Microphone one.
I know.
Yes, I would like to know what happened
to you.
Well, you pressured not to.
What happened to your laptop?
What happened? There was something about
exFAT and Michalos and
unplugging it.
OK?
And and my windows went
to try to repair a disk just freezes
like at
its heart
happened like one hour before the whole
thing started.
My second question.
Have you worked on the Xilinx
Spartan six series?
No, I never cared about the Spartan
ones and about the six series.
I only want
to reverse the seven series because of
the Cortex processor in it.
OK, thank you.
Thank you.
And Microphone two, please.
Yeah, thanks for the talk.
Can you comment on this like middle
point of the FPGA because you
have like this blackboard there and this
white part there?
Is it like the error correction code for
half of the FPGA and the other half of
the FPGA? Or how does
that work exactly?
With Heming code, you normally
mix the parity bits
into the data,
but of course, Xilinx doesn't
want that, so they put it in the middle.
And these certain bits that they are
already having called for one row.
I can show you later the details when I
get them out of my hard disk
there, I have everything
in details. With more details.
Thanks.
Thank you.
Microphone three, please.
I was somewhat puzzled by your remarks
regarding your inability to decompile
the Java toolchain you mentioned earlier,
because usually seashell up in the
sailboat codes and JVM stuff is
the easiest prey in that regard.
How come that might be,
but I always come a bit from a different
direction because I thought everything to
myself.
I had no idea how to take each other
with the letters toolchain.
I created two tours for
that called elimination.
One, for example, pitched
every single Trump instruction in the
binary so it could get the program flow.
Another one replaced everything else,
called breakpoint.
I then hooked the structured
exception, handling it from windows
and replaced every opcode
as it was executed.
In that way, I could reduce the
code by two thirds, which was
easy to decompile. But as I said with
Java, I had no idea how to tackle that.
There's lots of automated software for
that. Give it another
go. I never used it.
I always wrote my own software.
Maybe that's one
of the reasons.
Then we have a question from the IFC
chat,
what architectures
do FPGA is use?
You mentioned armed ones, but it wasn't
the FPGA itself.
No, I just don't use
architectures like
CPUs.
They have the building blocks like
the controller logic block
like Block RAM, DSP tiles,
the old tiles, and that's
the architecture.
Then microphone one again,
I am wondering whether
you have to try to extract some of the
device database from the video or some
information, or did you skip
that for for legal reasons?
I don't
know. I've thought about doing that, but
the binaries, I think, are
more than 10 gigabytes in size.
And I was like, No, fuck it.
OK, I think Vivaro
encrypts IP cores, so basically
virtually ellacott and they do the same
way. Also, for example, files which
contain some of the device information.
I think that's quite similar to what
Intel is doing.
OK. Are those who listen to the talk
yesterday.
I had no need for that information
because I could get
the device information out of like
10 or 20 example projects
just threw into the core.
OK.
If you want, I can show you later some
more details about that.
Mm hmm.
Microphone two, please.
Hey, impressive work.
Thank you.
Sorry for the presentation!
Uh, OK, so let's exclude
your presentation from your work.
Still impressive.
Um, my question was almost the
same, so you didn't look at X
or high speed
IP cores because it was too complicated,
I guess.
No, I didn't have a device for that.
Oh, OK, OK.
I don't have all
the hardware in my mind.
OK, thank you.
We'll ask you details later.
Microphone one again, please.
Did you do any work on cloaking?
What did you do?
Any work on cloaking like bills and clock
distribution and all that?
Yeah, sure.
OK.
Sure. I know about I have
some information about the column
drivers, the real drivers, how
everything comes together.
OK. But you but I was also part of
this class which have disappeared.
I had detailed
pictures of the schematics
where I could zoom in and zoom out.
But yeah, OK,
fuck up heaven's
microphone to please.
I think so.
I took my question
is regarding reprograming the FPGA
fabric from the arm cortex
us? Did you have a look at that?
Is it also possible with your work
or it is.
But another thing that interests me more?
The small thing the 17:20
I'm talking about has
two tiles that can
reprogram the whole thing or partially
reprogram it.
Mm hmm.
Yeah. And of course, results.
Yeah. So it wouldn't not
be a problem with flashing
that with your
selfmade file.
One thing about these and
the think it's a combination of a
CPU and FPGA,
but they're isolated.
You don't even need to power up the
J part, but you need to power up the
arm part because it's the arm part.
That obviously is prioritized and that
configure is the first bitstream.
OK. So I can just
use your bitstream then that you
generated using your tools.
I haven't, but I have
a very, very, very, very proof of concept
place and draw tool for small gates and
the bits with the IOC.
OK, that's working, and it's routing and
splicing.
OK, thank you.
Microphone one, please.
Um, what about the timing
information if you also reverse engineer
that
I started extracting the timing
information, but I wanted
to finish up more of the title
information before I
started with that.
But I have the tools already
waiting and that's that
would be one of the next parts of a taxi.
So sometime in the future,
we can expect to
actually use
it with timing analysis.
And I would hope to
because I don't have
a real motivation behind the
device other than for fun
if I could create something great
out of it that interests the community.
Oh, I would love to do that.
But until now,
I wasn't in contact with anyone
and microphone to please
so that you look at some other
features like the of scale plus.
Or maybe, yes, I did.
I started.
I started looking at the auto scale,
but before that I wanted to finish up the
seven series and I don't have
a working order to scale and I just want
to hold it in my hands when I reverse
engineer it.
I think you can understand it.
And the other part of the question that
you look at other vendors may be micro
small Terra Micro Semi.
I've first considered before I
decided to reverse engineered S40.
But I think that crap.
And yes, I really want to reverse
engineer the Otere into Leadpages
next, because then I
kind of regurgitated all the big three
vendors super things.
Thank you. And no one.
Yeah, I have a question concerning
the place and route you do.
And what is the basic approach
you take to reduce
become the nations of block placing
right now? It's just the proof of
concept. There is no reducing
anything later.
Of course, we'll use simulated annealing
and I really want to
get into a what way to call it the
reduced order
binary decision diagrams.
OK, thank you.
Number two, please.
Thank you for the questions.
You're saving me, I'm high.
Do we have and tried out
to get the bridges between the FPGA
and the hard car
parts working, for example, memory
or access from the FPGA
to the hardware peripherals in
the air?
I started working on that, but it's
just really interesting. Another tale
I can show you more to the later issue
of time.
Thank you. Number three,
how does the FPGA apply the
bitstream?
In what sense?
Well, you put it in
the Earth or something.
How does it
work?
There are several several ways with
this one because it has an ARM
Cortex processor.
So there's a small bootloader.
You can put the whole
thing on an SD card
and it loads it automatically through
the Cortex-A9.
Of course, you could use Choetech or you
can connect an external spy
device.
There are many possibilities.
Right? Thanks.
And we have a question of microphone for.
Hi, thank you for your talk.
A little request.
Could you present the whole presentation
in the self-organized session later?
Maybe.
I would love to cool things.
And number one again.
Yes, I had a question during your
studies. Did you discover
new stuff about FPGA
backdoors made by NSA
and friends?
No, but I found ways to
detect them
that
I found ways to detect.
Detect them.
OK. I'd love to talk
about you. Phone to you about that.
Sure. And I wanted to say
something else about
these families is visiting family you've
been working with, which integrates an
FPGA and a CPU.
I think that in terms of cybersecurity,
it is absolutely not a good idea to
mix in the same chip and
FPGA and the CPU
because an attacker like NSA
can easily upload some
a few bytes of cards.
No, he cannot.
And I will tell you later about that
because
I
have a I'm working on a proof of concept
for a and template device.
OK. I'd be delighted to
talk about that with you better.
Thank you.
We have a question in the IOC chat.
What is lacking to get a free and open
source FPGA toolchain?
Like with, we have storm for the IEC 4G
serious.
What do you mean?
Are the players involved to?
Wish I was 40, I gave Clifford
my findings and
tea together with some other guys,
they created the place and draw tool
and I just provided them with the
information about, Yeah, we've
documentation basically.
Hope that answers that question
microphone to please.
Yes, thanks.
You said that you don't do
very luck and we fiddle.
So what do you use as
input for your design tools?
The example project of the vendors.
Then I drank around the gates
to get some different
pacing and routing, and we're
sailing sailing's. You have to block
design editor.
I also had that in made a presentation.
OK, things
number one again, please.
Hello.
And between exiling it forces
you to use the Z4 bus
between the programable logic
and the arm cores.
Did you figure out if there's another way
to connect these parts?
What do you mean?
They don't force me to use the
bus death, although you are.
Do you also have like 64
year olds?
Oh yes, to get outside the device.
I mean, I don't know between the hours
between that and the fabric.
OK, good.
Thank you.
If you want to, we can show you more
details to the later, OK?
I think there will be a session later.
Microphone two, please.
Could you explain your way of reverse
engineering the FPGA?
Did you create a bitstream and observe
its behavior, or did you just create a
bitstream and not run it?
I never ran the bitstream I created.
I only once
tried a small bitstream I created by
myself, and that was
it.
So what are you to do if you did not run
the bitstream?
I just got the knowledge out of it.
I tried to recreate
the same that list information that I got
out of the tool chain only by looking at
the bitstream.
Thank you. And Microphone two
again.
Can you talk about reverse engineering
the non logic tiles
like the PLL tiles i o tiles?
Is that somehow different from reverse
engineering the logic tiles?
Sadly, yes.
You get the way
you get her. The information is
almost to no extent automated.
You have to look at or I have
to look at the schematic information.
Look what in turn, switches
are used.
Where do you go?
Then I have to create another image where
the switch is not used and I can
take the difference between the tile and
then. OK?
One detail Do the vendors
provide some sort of schematics of the
below blocks or is that?
Yes, we
provide information
with sailing's, you know, almost
everything about the device.
Cool. Thanks.
And another question in the IOC chat
when and where with a later session take
place?
When and where do you want it to take
place? I.
I'm not that good with talks, as you've
noticed, I'm more conversation,
guy,
so maybe you just come
to the front after just talk and
you can figure out a place together,
maybe at a bar or if there is
some free space.
It's it's a big space actually to.
Are there any more questions?
Doesn't seem like that, so give
a warm applause to a lesser.
The.