*35c3 pre-roll music*
Herald: The next talk is the talk on LibreSilicon project that's meant to
create a free and open silicon manufacturing process. And our speakers
today are leviathan, chipforge and Andreas Westerwick, creators of
LibreSilicon. So let's give them a firm round of applause and please welcome them.
*applause*
David: Oh, it works, ok. That's problem. That's what essentially is all this fuss
about is actually a description of how we... what this waver means and where we
will go with it. And yeah, I give now already over to Hagen which already starts
elaborating on the basic conceptional things.
Hagen: OK. Hello everybody. Hope you have a fresh mind. It could be heavy. OK. Let's
start. What we are. Last year David was involved at the project to looking for
free silicon, just a way to manufacture his own chips and figured out it's
difficult. You need a lot of contracts for that, NDAs (non-disclosure agreements). So
he looked around and find a clean room. We had to come in and say, OK, we can rent
it. Then he entered a scene on the last Congress - a lightning talk - and said, I
like to do that. And I wasn't in the auditorium there, but a guy told me later,
OK, look at this lightning talk. It's very interesting. You'd already doing chips. So
I entered in sees it or seen the talk recording and see it. Nice idea, I will do
that too. And the whole year we meet us by mumble. It's just a thing of distance you
know. David is located in Hong Kong. The clean room is there. And I worked from
Germany. So we exchanged e-mails. We talked on a mailing list. We built up a
small community for that and we had a first hackathon just to figure it out,
what we are doing with the tools, which tools are available how we can use them,
are they usable at all or not. And this was in May and during the process the
group wised up and already two of us got their qualification to enter the clean
room. The Hong Kong University is a little bit strict in that. You have to sit
there in the courses, you have to do exams and if you're fine with the exam then you
get the permissions to go in. So Victor which is on the most left and David on
the most right, they have the qualification for that and they
manufacture our wafer which you have seen there. It's a small one, but it's the
first stuff we have, right? OK. The basic points, what we are doing. We are using
a quite, let's see, old technologies from the 80s. It's one micrometer feature size.
It means a gate length of the transistor has one micron. It's not comparable with
all the processors you can buy now. It's quite old, it's really stuff from the 80s.
But we do it in a new way. We don't use the technology from the 80s. We do it with
the knowledge and all the experience from newer technology. Doing it again and using
some steps which are not so common, well, it wasn't common in the 80s. So why one
micron? One micron also means that the transistors are very robust against five
volt. Five volt was a usual supply voltage in the 80s, 90s and something like that.
Now the supply voltage is going down, down to less than one volt but for
tinkerers, for hobbyists, for makers, it's a nice value because older stuff, many
boards are still working with five volts and we're able to handle this voltage. So
we have a twin-well process; usually in the 80s there was just one well. OK, we
have to hurry up. We have three metal layers. We have interesting additions and
we are suitable for low tech. Ghetto tech, I would say. You can use it without
sophisticated equipment. We can analog stuff and so on and analog stuff means you
don't need small structures. OK. Areas where we have to work on. First, the
process. It's almost done. You have figured out it works with measuring. OK,
the next stuff: we need the tools. But the tools are also very old and mostly not
usable. We have to deal with that stuff. We have to rethink the tooling for that
and we need standard cells. That's my task. OK, so a couple of thoughts about
standard cells. They are very common. Usually, if you have a need to translate
your Verilog or VHDL and to bring it on a silicon you need small gates. NAND gates,
OR gates and so on. But these gates need a lot of representation, the combinatorial
sequencing. So OK. These are typical cells. Just a couple of them. But imagine,
we need much much more and there's design goals for the standard cells as we need
almost complete possibilities. If you have just this small selection of cells, the
netlist becomes huge and every gate in the netlist also means a dedicated delay. If
you have long chains we have a long delay so that our operating frequency goes down.
So if you have more complex gates we are better but doing all this stuff is heavy,
but we like to be lower power. That means our cells have to be consumption less
power than usual. We want to be fast but yes, of course, it doesn't fit all
together. OK. So we need it for simulation. We need it for synthesis. We
need it for timing. As you can see everywhere on the slides and, of course,
documentation. That's a lot of work. We are a small team. I am the only guy who is
dealing with the standard cells it's usually our teams also are doing that. So
OK, we need a tool for that which does all the stuff for us. And this cell generator,
I called it popcorn, because I put in some corn and it rised up with the heat. So we
can get all the representation. So currently I have this tool on the
repository which is Tcl which does some stuff I like, I need, but not all. But it
already seems very ugly. So for me I like to rewrite that but I don't figure out
currently which language I like to use for that. Next time it could be rust, it could
be scheme or something like that. We need another language for that. So if someone
would help - please, but that's the next task, if you have the wafer done
completely and measured. OK. That's a link for the repository where you can look at
the current status and there's a wiki where I like to describe why I'm doing
what in which way. But yes, we have to do a lot more. OK.
Andreas: OK. Hi. I take a look at the current tooling that exists like
layouting, place and route to minimize the yield on the wafer. And obviously because
this is the LibreSilicon project we look at open source tools. So we have Yosys and
graywolf, qrouter and several other FPGA routers that exist. Yosys is pretty good.
We can probably use this for the synthesis. But the other tools, they lack
very critical qualities for this... for silicon because they, for example, they
are part of qflow which is an FPGA workflow. So the graywolf tool, it
originates in academia. It's, like, it's many decades old. It comes with some very
good ideas, for example simulated annealing which is a meta-heuristic
you can use to solve NP-hard problems, but it's only one of the many choices you can
make to solve the extra hard problems. But it also comes with bad implementation, for
example inline syscalls is a very bad idea. And it's also written in C and blah
blah, OK. Qrouter is actually... it's pretty good. It started in 2011 by Tim
Edwards. It's widely used for, by hobbyists and enthusiasts to route for FPGAs. But
it's not ready for silicon and it's especially not ready for our LibreSilicon
process which would require us to to write a lot of C code for Qrouter. Also
parallelism apparently is not in scope, so I mean if we want to scale up, for example
place and route in the cloud or whatever or use modern CPU architectures, we are stuck
with sequential routing which is pretty bad. Also it lacks a very important
aspect, in my opinion, which is formal correctness. So when we produce wafers in
the fab we want to make sure that they don't blow up in our faces. This is why we
need some form of proof that our algorithms are correct and therefore the
result is correct. There are also other productive tools that are proprietary
where we can look at, but we cannot use it or fork it or whatever but we can learn
from the research that has been done, for example BonnRoute. BonnRoute is used by
IBM. The Cadence suite, I believe, is used by Intel and the Alliance tools is French
academia. Very UNIXy, I mean it's a very it's a very large set of small tools that
convert different file formats to another. I mean, maybe you encountered this problem
before when you did some hardware design; you have many different file formats that
all don't play together very well. So you have tools like X to Y which convert file
format x to y. And you see when you want to place and route and layout a very very
large chip, like a Very Large Silicon Integration, then this isn't even done,
like, automatically by tools. This is done with manpower. When you look at a very
large chip done by Intel or IBM. So this is an example of a very very large chip as
you can see. I mean do you think this has been done by automation like industry 5.0?
No. This is all manpower and a lot of manpower. Which we don't have, The
LibreSilicon project at the moment. So this is the state of the art is like
okay the manpower thing is one aspect but the other thing is so what you do is
you do placing and routing at different steps at the design process so you do
placing for a very large chip, floor planning and then you do a global routing
which is you /can imagine it like routing along a rough chessboard. And
after that you do a very detailed routing where all the different
constraints regarding your technology come into play and so again the formal
correctness aspect. So you have some imperative algorithm that you cannot prove
will blow up. And it's also not a very parallel code. So you're still stuck with
the sequential nature of the code and you have no parallelism. What we propose is to
not place and route for large chip but to decompose the large chip into much
smaller units like a component hierarchy or a sub cell hierarchy and then place and
route the small chips at the same time and then reuse the small units in larger
units. So you get an evaluation tree you can work on and compile just the
components you need. Also we propose satisfiability modulo theory solvers so we
can have some first order logic where we can have constraints on the components,
how they are placed for example they don't - they must not overlap.
Let's take the most simple example I will show you like later. And also we want to
achieve parallel or declarative code. So as you can see we have some, we have many
disagreements with academia and industry which work very well together for example
when you want to study semiconductor design you have to sign some NDAs with IBM
or Intel to do that. So, they say placement and routing or floor planning
and routing are different problems and they need to be solved at different times
in the process. And then all the components can be registers or NAND gates
it does matter they all treated the same. No it only matters that uh the floor
planning stand first and then the routing the closed routing then a detailed
routing. What we propose is that place and route is actually the same problem and
that registers are different from full adders. Okay. So the geographical
partitioning of a wafer is called floor planning or the placing step. And this
results in a cut tree. So this is how they do routing hierarchies. They just divide
the wafer into smaller pieces and then do the following steps based on this
placement. What we want to do is have subcell hierarchies and those sub cells
they are either explicit like they are explicitly developed for example the
rocket ship is very modular and it has many explicit verilog modules you can use
and place and route that and then reuse it. And it also has implicit sub cells like
for example most of the time. For example you have a full adder it obviously is
composed of one bit adders so you can place and route one bit adder and then
place and route based on the one bit adders that you artfully placed and routed.
And as a result you get a full adder. That's just one example but I will show
you a tree, a few slides. So there you see parallelism. There's something very
important for us. BonnRoute allocates a lot of research to have some mathematical
model for concurrency and shared memory models. qrouter, which is the open source
alternative, has none. I mean that's apparently not in scope. And what I
propose for the LibreSilicon compiler is the map and reduce approach. And as I've
mentioned you get explicit subcell hierarchies through high modularization.
That is done by the developers and you also get implicit subcell hierarchies
by compression-like algorithms that exline as opposed to inline the registers or one
bit adders. And this is also about preserving these newfound hierarchies in
the compiler interfaces so you don't end up inlining them again because this is
not a Von Neumann architecture where it would make sense to inline a lot of code.
So the code runs on the stack and the level 1 cache. This is about reusing
components. Okay. So this is a part of the rocket ship, the system bus is one
component of a very modular chip rocket ship. And as you can see it is composed of
several simple lazy modules and those simple modules are again composed of other
components. And then you have a lot of queues and this number on the left says
how many times it's been used. For example queue 15 is used 5 times in the
AXI4Deinterleaver and this is only the explicit hierarchy that is declared by the
developer. Okay. Now when you apply some compression-like algorithms you can
actually gain, you can get more leaves so you can be even more modular. For example
queue 1 is composed of several implicit modules and you can see one queue is even
reused seven times. So you just route, place and route these green leaves like
once and then you can reuse it in the queue 1 and everywhere where queue 1 is
reused some at some other point in the chip. Now I want to state a very simple
optimization problem. What we need for the process is to have components and
wires that connect the components or nets and these nets and components are actually
rectilinear geometries, the components shall not overlap and the nets shall
overlap with the respective pins they are supposed to connect. The minimizing goals
of this optimization problem is layout area, which is the most critical one
because this is what maximizes yield, the maximum wire length because it's about
resistance, the wire count you want to keep very small but you want to allow for
wires. The crossing number is a computational thing. It doesn't really
matter for the implementation on the silicon and you also want maybe you want
to minimize the wire jogs which is bends in the wire. So to to solve optimization
problems in 2018 maybe you want to use an abstraction from the SAT solvers. You used
to know academia came up with some pretty neat theory is called satisfiability
modulo theories and you can just put some first order logic and give it to a solver.
I've listed a few. For example ABC is used by Yosys and Z3 from Microsoft, also very
promising product, but you can obviously choose from many products by academia and
industry. Just a quick reminder what boolean satisfiability is: find
assignments for all these six variables which are boolean so that the whole term
is true. And now with SMT or satisfiability modulo theories you can do
the same thing but now with integers and also more complex data types but integers
are the most interesting. So let's do something with SMT. For example we have a
component that is rectangular. And now you can see this is like a Cartesian
coordinate system and you have the left bottom point which is x and y and then you
have the right and the top point. And now if you for example have this problem that
you don't want to have overlapping rectangles you can have a rectangle A and
rectangle B and declare these coordinates and then have some proposition that shall
be true and to have a proposition that says they shall not overlap is to say
this. I mean it's actually the lower half that makes sure that they don't overlap
and the upper half makes sure that the components actually have the right
dimensions. Well in this example they obviously have the same dimensions the
same components. And so you make sure that the left point of the second
rectangle is right of the... Okay no, never mind. One last important point I
want to make is that this this framework we want to create, it's not based on the
inheritance model that we've seen in the process steps right now. But we want to
combine the problems. For example the overlapping problem, the pin connect
problem, and then arbitrary constraints that come up during the process
development that Dave and Hagen will supply me with and I will formulate that
in first order logic. And then this makes sure it's formally correct and it
doesn't blow up. And as you can tell I mean I've combined many NP-hard
problems at the same time but I think we can manage that if we have very small
cells so I'd suggest we just stay here and don't do all this for very large chips but
reuse small chips and then reuse the small chips in other small chips. The silicon
compiler is one half of maximizing yields. And the other half is to get the
process right so to get the process right, we have David and Victor. So please.
David: So thanks for the handover. So very first. There's a lot of questions why Hong
Kong. So one thing why this is a really suitable place to do that is
because of history like the epic Commodore 64 has been made in Hong Kong. Then the
chips in the first Macintosh have been made in Hong Kong and all of these
manufacturing lines. Some of them at least one is still available. So also there is a
very advanced laboratory. That's the NFF, Nano Fabrication Facility in
Clearwater Bay and they let us kindly use their equipment to develop this process.
Also one of the sectors I mentioned before, RCL semiconductors, they're really
open to introduce LibreSilicon in their mass-manufacturing lines: one in Shenzen,
one in Tai Po. So in conclusion of that we have advanced R&D labs there. There is
factories available. We can easily export it to here over channels which already
exist. Right. And also in general it's just more relaxed over there. And I don't
like minus degrees. So our process is a little bit of a monster. So it makes sense
to tackle that one by one so we are right now feeling ourselves upwards to get the
standard CMOS debugged, final with optimized frequencies there. But we
already have on the Pearl River, I've shown you, we already have test structures for
high voltage MOSFETS, B junction transistors, Zener diodes, even flash,
resistors, and caps. So it's only a question of effort I guess in the next few
months to get that working. When we designed the process like, how it usually
works when you make a process, you look at the machines you have availlable, what can
these machines do, optimum operation range and then you look what substrate, what
material you have available and then you start tinkering you own little proprietary
process. That's how fabs do that. And we said, OK, well, to the point where we look
at the machines - what can they do? We do the same, but afterwards we look that
it's portable. Not specific to the equipment. So just because we have certain
machines which can do awesome things, but are really exotic, doesn't mean we have to
use them. So we avoid exalting machines so that it's as portable as possible. And we
also try to use wet etching whenever possible in order to make sure that you
even can build it in a basement. And here Evan Heisenberg may be interested now in,
you know, changing business into a less dangerous business. And, yeah, they can't
be leading the innovation hub Hamburg I've seen, like this improvised clean room with
just a diffusion furnace. So, that's a cross-section of the... it's not
finalised, but you see a cross section theoretical that's... by the way, you can
find it on GitHub as well. It's all in the publications, everything we develop, all
the measurement data, all this on GitHub. So that's actually the layout of these
little squares here on the wafer. You see the apple in the middle. It's just in
this year. That's, uh, it's nice. I have a Python script in the GDS2 generator
tool folder for Python and you can take any png or anything and just
convert it into layout format, so you can put your own pictures onto the metal free
layer. So in case you already have interest into making little trips also.
It's also possible to make, like, ear rings also with ... We don't care as long
as there are 4 more millimeters on the silicon. You can put pictures on the
silicon. So that was the Pearl River right. And the Pearl River fulfills the
function for us at the moment to debug all the features of this LibreSilicon process.
Then the next thing we have to use it to calibrate new foundries so now, we
developed it at the NFF in Clearwater Bay right. And afterwards we go over to HQ
with, to the RCL guys in Tai Po, and they have the machines and then we have to pipe
the Pearl River layout through there as well and repeat that process over and over
again until the measurement data, like the frequent, the you know the Beta
depending on Omega of the transistors and the resistance of the wires and everything
kind of is the same as at NFF so that you can basically, as I mentioned before one
of the design concerns is portability that you can basically prototype a chip
at the NFF and then produce it in RCL or in maybe some other fab in Shenzhen or
whatever. And so and if there are new features coming out which also make a new
release of the Pearl River test waver and we give that around they push it to GitHub
and people can introduce and calibrate the process to support the new feature. And so
that's how does that work. So usually, typically you have something like a photo
mask like here. I didn't bring that one because it's in a clean room there and the
dust might scratch my micro structures on there. So also afterwards I have to clean
it for half an hour and when I come back to Hong Kong from here I'm so jetlagged I
just want to get started again, not wait for the mask.
But there's a picture. And these masks,
usually a stepper/aligner specific. If you don't have a stepper then you need to make
a direct transfer that means you actually have to put the chips in the size you
want to expose them directly onto the mask. Then press the mask onto the
photoresist, expose and develop. That's messy because you have to clean the mask
all the time. And it really depends. So actually you can do exposure even without
a stepper. So we actually really could do it also there in this university lab in
Hamburg. So all you need is a new UV light. *laugs* So we have a little bit more
advanced tech in Hong Kong. So we have here an SVG coater, this baby dispenses
automatically HPR 504, a resist. So we actually just have to put in the left, you
see the cassette slot. So you put there like twenty five wavers or so and then you
have a receive slot and put another cassette there and it just starts sucking
in the wafers one by one, puts primer on it, soft bakes it, and easy. Then you
expose it, develop it, hard bake it, chilled. We have two types of resist actually
and the 6400L for the implantation unfortunately has to be put in manually.
So it comes and it gives you 10 seconds to open the chamber and put the resist on
it. In both cases however it doesn't really matter so much because the
thickness of the resist is depending on the RPMs of the spin coating unit. So you
just have to kind of put two thirds of the waver should be somehow covered with the
resist and the excess resist goes away. But you have to control the RPMs because
depending on when you do wet etching for instance and HPR 504 has to be enough
thick because of selectivity, so that you don't etch and consume the polymer,
the resist. So you have to make it thick enough that you don't have,
you haven't consumed all the polymer before
you have etched your structures. And the same goes for the implantation because you
need 6400L, this one can sustain higher temperatures so you can use an implanter.
Now afterwards after exposure development it looks like that. That's an alignment
cross for our optical stepper and for instance that's our ring oscillator. So
it's one of the structures on our Pearl River actually. So N well, P well. I have
to hurry up, only 10 minutes or so. So that's a picture of the developing we have
some P well mask developed so we have everywhere resist except in this little
crosses and stripes there. That's there below is the silicon where we implant. The
recipe is easy, first coat, expose the implant and then resist strip. Same for
the P well and after the resist strip you can put it into a diffusion furnace in
the atmosphere for like four hours. So where does the four hours come from? So
we have the Fick's equation. And the Fick's equation is essentially in a
similar shape like the laplace heat conduction equation, so to solve, there
are already nice solutions for it. So for instance if you use boron or phosphorus
which has the nice property that they have the same constants for this Dₑ. So if you
have the same temperature you basically have the same Dₑ for phosphorus and boron
so you can implant them next to each other and then put them at once into the
diffusion furnace and the wells are the same depth. So that's why these two
materials are usually used for diffusion. So that's one of the solutions that you
get, the surface for doping for the threshold equation which I also will rush
through in a moment as well. The equations you see here with background
doping it's a little bit much. As you have here this natural logarithm inside. But
besides that you see this jump and that's how you essentially build a well, you have
the background doping and you compensate the donors and acceptors with each other
so that's what this absolute value of the difference means. So the threshold
equation is pretty easy. And like basically mirrored for PMOS and NMOS that
just like mirrored in the sense that one of the transistors as PMOS is built on a N
well and NMOS is built on a P well. Right. And what essentially controls the
threshold voltage, so the operational voltage, which usually in the standard
CMOS is around 0.8 respectively minus 0.8. That's doping here like the donars
respectively acceptors and the q as usually that's the oxide charge. This is
usually a process specific constant but that can change. And then you get
flash, it can change Q_SS and then it's flash. That's what you use in SONOS
flash, stands for silicon oxide nitride oxide silicon. So there you have a
standard again, NMOS in this case but you have a sandwich instead of a normal oxide
layer and for the gate oxide you have a nitride and oxide. These oxide layers
above and below the nitrate are called tunnel oxides. And the trick is that with
high enough energy you tunnel electrons into the, through the oxide into the
nitride where it's trapped and then you shift the operation voltage, the threshold
of the transistor. And when you then put one at it it doesn't turn on anymore and
that's essentially how the most used flash solution besides normal floating gate
works. It's really simple. So. And after you get your wells out of the furnace, so
I did a little detour. You want to make sure that the lateral diodes which got
into existence after diffusion don't create unwanted short circuits. So we use
the technology actually developed much later after one micron already has been
out. It's called STI shallow trench isolation. It's from the ULSI technology
as well as the silicide we use to reduce the resistance of the polysilicate.
Here are some pictures, we did etch this one in the lab. That's the islands so that
around everything going down that's the trenches in between the gates and between
the wells. So we isolate them from each other. So the recipe is pretty easy.
So either you have a plasma etcher around or if you're not
rich and don't have money to buy a plasma etcher from eBay you can also get this
tetramethylammonium hydroxide. And it's not even the german name, so cool, and
dilute it with deionized water 3:1 and this 25% TMAH solution you heat
it up to 80°C, dip your wafer in for six minutes and then you
would get your structures. Metal is easier. So we did here the metal
interconnect for the ring oscillator. They're etching it, also you make a
vacuum, deposit 100 nanometres aluminum, 30 nanometers titanium for passivation.
Take the vacuum away dip it into HF until you don't see streaks on the titanium,
then into aluminum etchant until you don't see streaks from the aluminum. And then
you have your wires. I'll skip that one. That's just really interconnect.
But I plan to make videos soon where I go through the you know like daily video blog
of results but just that you see that you see the oxide depending on the angle it
has different colors. So that's L2 the isolation. And then you see the
topological measurement device. You see this one micron because we only deposited
a micron for now. You'll see the heights the differences and we see that one micron
is not enough. So we'd still have these sharp edges which we don't want. So we have
back in Hong Kong have to deposit another 2 microns. And if you want a follow up you
go to my Github. OK? So Victor that's him and I have done that so far. It's only
like two weeks because it took a lot of time to get all the masks manufactured and
so a lot of bureaucracy. We already have that much and just stay tuned. We already
have figured out so much in the last two weeks that it shouldn't be long before we
can well finish all the features of Pearl River. Create models with Hawkins popcorn
and start figuring out all the analog stuff for our MCU and then we make
an MCU. That's the first thing we want to do as soon as we have the features figured
out of Pearl River. If the Goddess is nice to us. Yeah it's a discordia figurine,
it's really cheap on ebay. *laugs* So yeah. And that's like an overall
of the features. And we want them build this microcontroller, and yes because all
the folks don't believe that there are people who want to buy such items you
please fill out the survey. That one is from Hagens trip, i skipped it but
yeah. So yeah. Thanks. I'm done. And too late but sorry.
*applause*
Herald: Thank you for the talk. No, but if you wait we have time for questions. So
there are two microphones. One is in the middle and one is on the left side of the
stage. Line up and we're going to take some questions and there is already one
question from Microphone number two. Microphone 2: OK. So thank you for that
interesting talk and all the development that you're doing. I was wondering have
you had any time to test your transistors yet. And then later on do you plan to
release some sort of analog simulation capabilities.
David: Yes. Thats the plan for the next few weeks after I'm back in Hongkong. We
did go back to the cleanroom. We actually wanted to provide already something for the
Congress. Unfortunately we were noticed, short noticed that Thursday and Friday
they take the wet stations and the machines offline for maintenance of the
AC. So we have already like, the wafer, we have the isolation oxides but we didn't
have any time left to actually test the the you know only having polysilicon is
not enough. You have to also have metal to go with probes there, that stuff is
micron size. Hagen: Okay. So your question as I
understand was in the direction of simulation right? We like to measure all
the structures we have to produce and with the values we get we like to feed in spice
models. So you can do analog simulations. And yes we like to use this technology for
analog stuff because as I already mentioned one micron size is enough for
analog. You don't need smaller structures. Analog all this having huge transistor
size from 20 or 50 Microns. So they are huge, you don't need this small
technology. So they are quite feasible for analog stuff but let's say in this way if
you're doing analog stuff in a conventional way you have to sign all the
NDAs and you're stuck on this technology you're using. You can't transfer your
design to the next fab because in the next fab the PDKs are different. You have to
transfer or to translate all the structures there for a rebuild again for
the new technology if you have a technology which you can take from one fab
to another like our one. You are quite happy because the analog stuff you
designed once also fits for the next fab. So yes of course we like to support analog
stuff. We need help for that of course we have to measure, we are currently
developing the wafer, we are currently working on the documents how to measure,
what we like to measure and then we have to transfer the values to spice. But we
have documented how we are doing that. And so everyone can use the knowledge.
Mic 2: Thank you. Herald: Thank you. Mike one please.
Mic 1: Do you have any plans for open source mask production like.
David: Yes. Actually the problem is only that as I mentioned before. If you want to
have an opto mask for steppers that's always manufacturer specific. If you want
to have a direct transfer mask not a problem. So I guess so Sam is really
helpful in the lab. He runs the laser scriber. We could talk with the folks at
NFF. They were really lovely helpful really. They really like to really help us
a lot. And now that we talk with RCL. They also have laser scribers that we could
actually also start producing masks in the long run. So yes that's certainly one of
the things I intend to do is providing optical masks for exposure. Um yeah.
Herald: Thank you. Uh one more question from microphone two.
Mic 2: Great talk thanks. I'm really interested in the - what it would take to
build the fab. What's the minimum set of tools. We've already seen a couple of
orders of cost reduction in, through DIY bio hacking by making the tooling a lot
cheaper. Do you see that happening within the nearest decades and your sort of work?
David: Yes. So for instance I made my process by purpose this way that you can
actually improvise most of it like the LTL growing and deposition and everything with
a furnace. So what you need is a wet etcher like some wet etch station. You can
actually there is a video from Jeri Ellsworth called "making microchips
at home cooking with Jeri" and he does microchips in the kitchen so it's
not, you get scared like HFS, it dissolves your bones and so on and then you see the
guys who already have qualified, are qualified or employed there: they just
without any PPE, nothing just grab into the HF. That's just the skill to scare
folks from generating insurance problems. In general it's not really that dangerous
right. You can do the stuff at home. No problem. Yeah. So we intend. So this
process I made is so trivial. So we have also a branch called super low tech. We
just shall essentially but it's more RnD. But you could actually help there for
instance figure out the last details, get a furnace from eBay put it onto your
kitchen table start RnD-ing make some git pull requests and we're super happy. Okay.
So it's doable and the furnace you get on ebay. So no problem.
Herald: Thank you. Microphone 1 again. Mic 1: So you just said about the
analog stuff that a lot of that is usually under NDA from the fab. So have you
encountered any problems with the fab and that you're currently using in that you're
actually trying to discover these processes for yourself like you're
generating competition that they might not like, have you had any problems with that.
David: Oh no I had a nice phone calls, e-mails with the owner of the fab over in
Tai Po who also has a second branch in Shenzhen that's RCL. I actually asked him
recently "Hey is it okay when I use your logo in the presentation and implicitly
make an advertisement for your fab here?" No prob go ahead. That is like...
He's really eager to, LibreSilicon is what they need because every fab
usually has to invest money in to develop it. First they develop a proprietary
process right, or they license some proprietary process from another company
and then they have to invest RnD costs to develop IP cores for their setup. With
LibreSilicon the problem is solved for the companies because these foundry is
using LibreSilicon everything the community develops is on github. And
that's the IP catalog essentially. So they don't have to invest any
additional money into RnD-ing IP cores that's in the nature of open source that
there are IP cores popping into existence all the time. They can focus on the thing
they're best at: making silicon, right? So it's actually positive but only for the
small foundries that are really interested especially Shenzhen and now some in India
and some of the big foundries and they will not, they are anyway the big
companies have the tendency to be as mobile as a cargo ship. So it will take at
least like two years until they acknowledge that LibreSilicon exists and
then we might expect some legal you know bullying. But for now they won't even they
just laugh right. They just laugh at best.
Herald: We're going to have two more questions before we're out of time.
Microphone 2. Mic 2: Why did you go for the twin well
process as opposed to the simpler single well?
David: Uhm that's a good point. That's also something with portability and if you
have different events or different supplier for substrate it might be that in
n-doped or un-doped substrate. So with twin well architecture and actually we
have on the n-well we also built p-bases and in these n-bases, so we have actually
like stacked wells in the n-wells and p-wells. So actually it's a one two. Um
Pentagon Well I don't know. Um and it's just that you can shift to
the doping of the n- and the p-substrate. According that you fit LibreSilicon
requirements to still have the physical properties ensured by LibreSilicon. No
matter whether you get your substrate from somewhere from Great Britain or from
TaoBao. Hagen: Okay. The thing is we looked before
at eBay which wafer we can get. Currently NFF is supporting us with wafers. But if
you're looking on eBay or Alibaba. What else. We get different wafers with
different dope agents. And if you have something with say OK
we're just building an n-well we have to verify or lie on the p-base right, or on
the p-substrate. And to avoid the obstacle the difficulty is: we're doing twin-wells.
We can just regulate our own dopant inside and we are fine. We don't want to have to
rely on the wafer or substrate itself. What was the basic point.
Herald: Thank you. And the last question from microphone 2.
Mic 2: So once you have your complete die how about packaging and bonding because
if you want to use it you have to place it somehow on the PCB.
David: Yes. So um. We have a bonding setup at Tai Po already. That's what still is
being used at the moment in Hong Kong is to bond a packaging. Then we have some
guys in HK SDP with packaging set up they have and can make nice tape reels and they
have also like uh after packaging tests like: did the bonding work, is it damaged
by the bonding, and so on. Hagen and I have figured out some nice bonding pad
design which didn't fit at all anymore into the talk I already over talk like
that. And but it absorbs the physical stress from bonding. So we think that
it's aluminum covered with titanium so you don't have to sweat away any oxides right
you have better bonding capability, better bonding properties. So it shouldn't be
such a problem. And we have plenty of bonding and packaging labs which have
already promised to help us. So it's really like small like to choose which one
we take. Hagen: Just an annotation if you like a
dedicated package please mail us. Right. We are fixed now on the dual in-line
package. We are thinking about flip chip BGA but if you have other package which is
more common for tinkerer or something like that please mail us.
Herald: Thank you. Thank you for the talk. That was the talk on LibreSilicon,
leviathan, chipforge, Andreas Westerwick and Victor. Thank you. Thank you.
*applause*
*postroll music*
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