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our first Speaker of today is Marx
Hoffman he is a researcher at uh the
embedded security group of the um horse
gz Institute at the rural University of
bom and also associated with the max
plank Institute and we'll speak about
Hall The open- Source Hardware analyzer
a dive into foundations of hard reverse
engineering Anon and netlist Analysis
framework Hall he will introduce us to
the uh foundational levels and the
challenges of hard reverse
engineering and discuss what he research
can be done with the whole framework
that he and his team are developing
please welcome him for you of
Applause yeah welcome also from my side
uh welcome to all the people that are
here this early and also welcome to
everyone at home watching the stream um
so how to start the final day of uh C3
um and I start I thought let's start
with a quote uh trust me I'm an engineer
this is a very famous quote by basically
every engineer um and um if we look
what's out there if we look at the real
world uh the quote is proven right yeah
we see countless example of great uh
great Engineering in the wild and uh
these things they they make us Wonder
yeah they are great um all these great
examples of engineering out there um
they they focus on so many areas but uh
for all of us here like technology is
one of the main focuses of engineering
that we are uh looking at and if you
think about it like our current
technology level all of the stuff we
have experienced here over the past 3
days and like the whole world at its
current state it's driven by technology
and this is the result of years of
engineering
so if I was asked to Define engineering
I would say engineering means turning a
high level description into an actual
thing and this is like a very handwavy
definition but I think it captures quite
well what what an engineer does at its
core so humanity is driven by curiosity
we want to understand things especially
if they are
fascinating so how do we understand the
complex works of
Engineers you don't get engineer uh you
don't become an engineer just by
watching a few YouTube videos like years
of training go in there um and all this
expertise how can we understand this how
can we learn from this and the most
simple answer is by talking yeah we ask
Engineers we talk to the teams that make
all these things but what if no one is
there to teach us or no one wants to no
one is allowed to teach us well then we
have to take a look at this ourselves so
if the way from the high level
description to the thing is engineering
we are interested in the way back and
this is called reverse engineering so to
put this into perspective or in our um
definitions um reverse engineering is
analyzing a thing to recreate a high
level description and it's important
that it says a high level description
not the high level description um as we
are not always interested in the exact
high level representation uh that
resulted in the thing we are analyzing
but maybe just in an approximation or
something equivalent and if you think
about it we have all done some form of
reverse engineering in our daily lives
no if you uh think about your your car
if you have a engine failure um you have
to look at it and you did most likely
not build this engine so you have to
understand how it works and this is
already reverse engineering or even more
abstract if you eat a delicious cookie
you want to know how the cook made this
cookie what are the ingredients what was
the recipe so you go from the thing to
the high level description but this
presentation is not about cookbooks it's
about Hardware and more specifically I
want to talk about chips so all these
microchips that you find in your
smartphones your gaming PCs and so
on but uh like a more fundamental
question is why would anyone even want
to do this why would you want to look at
chips and how they are made well
curiosity of course yeah but uh you
might also want to understand or locate
errors just like in the engine um if
this is a chip that has already been
produced and passed all the test tests
then you might have to take a look
inside to find errors um also from a
legal perspective you might want to
detect if someone used your third-party
design that you uh developed uh without
paying the license fees so you want to
detect patent
infringements but there's also like um
so these are all benine use cases but
you can also take a different approach
so of course you might want to detect
Trojans that were inserted in the
circuit but on the other hand you might
also want to insert Trojans into the
design and um on a much much much wider
scale you might want to just clone or
steal intellectual property and also for
this you have to um do reverse
engineering and this is also something
that came up in media over the past
years so for example you might remember
the big hack um a story that was
published in Bloomberg business week and
um just as a disclaimer this were
allegations so nothing of this has been
proven true there's been a lot of
discussion but no definite statement in
the end but what they claim to have
found is um that in server Hardware um
of the company super micro that was used
by Amazon and apple there was a hardware
implant an additional tiny chip on This
Server board that allowed for backdoor
access or remote access and in their
image it's located in this white circle
yeah this tiny thing um was the hardware
back
and um they claimed that it was inserted
during board uh fabrication so putting
all the parts together on the board in
China um and the interesting thing is
they claimed that this chip that was put
on there looked like a passive component
so it didn't look like a chi it was
camouflaged you could say uh to look
like something uh passive but it was
actually actively interfering with
Communications and then also we have the
uh telecommunications ban by the US
government uh on on China
telecommunication uh equipment um so the
whole Huawei debate which is still
ongoing um in uh yeah in this days so in
this talk I want to give you first an
introduction to the basics of reverse
engineering but also into the basics of
Hardware engineering and and to
understand how we can go the The
Backwards direction we have to take a
look at forward direction as well then I
want to talk about hell Hardware
analyzer and the research that we do at
the institute at the University um
associated with hell but as a disclaimer
this is a foundation talk so I do not
and I cannot make you experts in such a
short uh period of time but I want to
give you a high level overview so that
you can get the big picture that can
that you can talk to others that you
understand the underlying principles and
difficulties of Hardware reverse
engineering so let's start with
engineering Hardware design um since I
guess that most of you know their way
around software pretty well yeah um but
Hardware is most of the time kind of
difficult I will try to make analogies
to software as often as possible to make
it like more understandable for you and
in this talk I will focus on two kinds
of chips two kinds of integrated
circuits the first one are A6
application specific integrated circuits
and the second kind are field
programmable gate arrays
fpgas so an Asic is basically your
classical integrated circuit this is
what you think of when you hear chip
basically it's optimized for a dedicated
purpose think about a sensor or
something and the logic in it is
implemented um through Boolean Gates and
flip-flops and some other elements of
course yeah but these are the the main
the core elements that comprise an
Asic n of PGA is reprogrammable Hardware
the ASC is fixed once it's built it does
what it does but you cannot change it
anymore and the fpga of course the
hardware in the fpga itself is also
fixed but you can reprogram the as uh
the the fpga so it is optimized to offer
you a high degree of freedom for
reconfigurability
and how how is this done well the main
elements that are reprogrammable so
accessible by you are lookup tables and
rooting elements and you can now think
about how to um Implement Logic on this
Hardware you will just take your
functions your your logical functions
you put them in the lookup tables and
then you just connect the inputs and
outputs of these lookup tables uh via
the rooting elements as you like and
this way you get reprogrammable Hardware
so you have Hardware that is kind of
dynamic but you still uh you can change
it you get all the benefits of
programming um but the parallelism of
hardware and for both of these
architectures we have to start somewhere
when we want to design them
and this start is kind of comparable to
a programming programming language it's
a hardware description language HDL and
just as an example it looks like this
but there are many Hardware description
languages out there and these this code
that you write it describes the hardware
you want to uh have in the end so this
short example here it uh describes this
circuit diagram a full
Eder and um now um if you think about
software again the compiler that you use
has to work with a specific instruction
set So the instructions that your Prof
uh processor provides um the compiler
has to break it down to these
instructions and we have in in Hardware
we have something similar and these are
called gate
libraries and such a gate Library simply
contains all the elements that you can
use for an fpga it contains all the
programmable elements so you know what
you can work with and for A6 it
describes what ever um can be built from
transistors because transistors are like
the um the underlying element everything
is built off
here and um another diff difference from
software is that software is compiled
for most most of the time but HDL gets
synthesized and this synthesis process
can be broken down into three major
steps so the first one is architectural
mapping where you take your description
and you map it onto the elements of the
gate Library what you actually have yeah
and the second step is placement you put
all these elements on the area that you
have and then there's rooting you
connect all these elements in the most
efficient uh way and the result of this
synthesis process is called a net list
and this net list is the central element
that we will talk about today or that we
will focus on so to put this in a
picture you start with the HDL code you
run through synthesis and in the end you
get your net list and what is this net
list well think back to physics class
these circuit diagrams you all had to
Drew to draw um these are basically A
visual representation of a net list now
just replace the light bulb and the
battery with like um digital design
elements and basically you're done the
net list contains the whole design it
contains all elements that we use all
Gates flip-flops and so on the
interconnections and additional
information let it be like position of
the uh of the elements Drive strengths
of gates and so on so again to make the
analogy to software this net list is
somehow comparable to assembly in
software now let's take a look at our
big picture so we know how we get from
HDL to the net list through synthesis
but how do we go to uh fpgas or as6 how
do we end up there so let's start with
fpga as I said the fpga is
reconfigurable and we want now to get
our net list into the fpga and this is
actually kind of straightforward we take
this net list and translate it into a
configuration bitstream it's called
bitstream for fpgas and this
configuration simply maps all of the
elements in our net list to the fpga
elements and then we put this uh
bitstream onto the fpga it configures
itself and we are set
perfect so now let's take a look at A6
here the story is quite quite different
because if we just take a look at this
circuit diagram we immediately encounter
a problem how do we manufacture this we
have a crossing of wires and if we would
just like lay them out and build it like
this um we would have a short circuit um
so the solution here is to work with
multiple
layers and um this picture shows this
quite well you basically put all your
logic so all your computational elements
storage elements you put them on the
lowest layer and then all the layers
above you only use to connect them for
rooting and uh you can see the the metal
uh lines up here these are basically
what you can think of as the wires on a
single layer and those uh orangy lines
these are called vs vas interconnect
layers and this is uh what we call a lay
layout and this layout that represents
our net list our design that we want to
have this is sent to a Foundry for
fabrication so in the end in our big
picture we now know how we can get from
HDL over the net list to either in F PGA
or an
Asic so after this brief overview on
Hardware design Hardware engineering we
can now take a look at reverse
engineering but again as always we take
a look at software first and in software
you usually start with a binary or if
you don't have it you have to extracted
from some kind of memory so you have
like an extraction phase that sometimes
is very short and then you start by
going back to the assembly and maybe
this is enough but maybe you want to go
like a step further and reverse
partially the the high level language
this was written in so you have an
analysis step and basically we find
these steps also in Hardware but they
look a little different
so in our big picture let's start with
fpga
first as I said the fpga is configured
using the bitstream and the bitstream is
somehow put in there but how do we get
it out well it turns out in reality um
it looks more like this that an fpga is
configured through an external flash
memory this is true for the majority of
fpga so we actually don't have to bother
with the fpga at all we just have to get
the contents of The Flash memory out and
then we have the
bitstream but how to get from the
bitstream to the net list well as I said
earlier the bitstream is just a mapping
of the net list elements to the fpga so
it's a different
representation and if we understand this
format of the bitstream we can just
translate between the representations so
we can go from the bitstream back to our
net list and we are done
nice so what remains is the Asic how to
get from the Asic to the net list and
this is a different story because we
know the forward engineering way we know
we have to get to the layout we send it
to a Foundry and The Foundry then
delivers us the as6 somehow but how do
we get back do we actually like we don't
go back to The
Foundry so if I say chip this is what
comes to the mind of most people but
this is not what actually
computes if we take some uh asset for
example and remove this so-called
packaging that we have here this is what
we see and this is the so-called Dy and
the Dy is the thing that actually
computes the Dy is also the thing that
gets fabricated by The Foundry packaging
is an extra step and you can see these
tiny golden wires that um reach from the
um ioads of the die they are connected
to the silver pins that you see on the
package and that you can use for
soldering so uh the actual D the heart
of the um package this is what we are
interested in in reverse engineering and
if you think about it this die is
exactly what we sent or what we
specified with our layout files so how
do we get from this physical thing that
we have in our hands to this layout to
this layout or maybe like immediately a
step further and the solution is quite
simple we take sandpaper and a camera
well it's actually not that simple
but the process uh can best can be best
explained that way you take your D and
you take a picture of the top layer of
the D and then you um combine like a set
of chemical or even mechanical edging
processes to get rid of the first layer
and you take another picture now of the
second layer and also you want to take a
picture of the vs in between and then
you repeat this for all of the layers of
your circuit of your of your design and
in the end you have like a a set of
images with an image for each
layer but it's not that simple because
in current uh technology sizes Optical
micro microscopy is not sufficient
anymore so we make use for example of a
sem a scanning electron microscope and
they have a very very small area they
can scan so actually for just a single
layer you get like like thousands of
pictures and uh the sem always has to
move its focus to the next position so
in the end you not end up with like a
few pictures of the layers like modern
chips have something of like 10 14
layers um or even more um you end up
with like thousands of images that you
now have to put together you have to
stitch them you have to align them and
then once you have a perfect image of
each layer you have to also align the
layer images on top of each other
so to put this in more formal terms than
sandpaper and the camera the first step
we do is decapsulation get the D out of
its package the second step is
delayering and this is interleaved with
imaging so always image delayer image
delayer image delayer and in the end we
put all of these images together in some
kind of
postprocessing and then if we analyze
these final image stack we get to our
net list finally yeah so to get into our
big
picture getting from fpg from fpga
content so from the bitstream to the net
list um is done through format uh
adjustments or format translation and
getting from an Asic to the net list
involves like a step of quite complex uh
a series of quite complex steps so you
still might think now okay I think I've
got this yeah I mean all the steps seem
quite clear although like uh I I
summarized a lot
um where's the catch and I want to now
highlight a few of the like hard
problems we have here so the first
problem is these steps of Asic to net
list they are very complex they take a
lot of time they take a lot of expertise
they are costly um the equipment itself
is very costly and the engineers that
have to work with this so this is like a
major major um
Step second problem the gate libraries
for as6 and uh for fpgas the bitstream
formats they are proprietary most of the
time so we don't actually know what all
of this stuff maps to or what it
does and the third problem you might
think about is uh if I say now net list
as I said circuit diagram you might
think about something like this yeah but
a real net list looks more like this and
to be fair this is a very very small net
list this just shows an AES circuit
roughly 6,000 elements and also the
wires you see they uh they are
aggregated so one of these wires might
transfer eight bits but in reality you
would have eight separate wires in this
place and this is a mess how do you work
this work with this yeah and how do you
cope with these problems but um if we
take a look at the problems again like
for the first problem specialized
companies exist there are companies that
do all of these steps for you
also there's ongoing research how to do
this like better faster more efficient
so um there's a lot of stuff going on
here and also gate libraries of A6 can
be reverse engineered on the Fly because
the gate Library specifies like the
small things that we can use an endgate
for example and now if you think about
it we just look at a few transistors
figure out what they do and then we use
pattern matching to find like duplicates
in our uh images then we can can quite
efficiently um get this on the Fly and
for bitstream uh formats there's
actually like a lot of ongoing work that
tackles this that takes a look at how
can we get this bitstream format um for
interoperability for example so the
remaining open problem is how to reverse
engineer a net list and this is also the
the core question that we tackle at our
University so we don't uh really tackle
the questions that came before we don't
look at how to get from Asic to a net
list we take a look at how to reverse
engineer such a net list how to
understand it and if you remember an
nlist is kind of comparable to assembly
so let's take again a look at software
where we know how to handle assembly and
we have powerful tools for binary
analysis we have Ida Pro for example or
gidra but we also have open- Source
tools and Frameworks that can be
extended by plugins and all that stuff
so we have a very rich environment um if
I have to put this in a picture it would
look like this yeah we have a lot of
options and a lot of people that are
going there and trying things
out well this is the situation in
hardware and um it looks quite bad yeah
there there is none such tool available
there's no Ida there's no gidra and also
very little people are actually doing
Hardware reverse engineering because
they think that the entry barrier is
very high high but luckily there is hope
roughly four years ago at the beautiful
Ru University bom in the ID building we
started a project that is now continued
at the max plank Institute for cyber
security and privacy in bom um and my
former colleague Mark fbak he took a
look at the state of Hardware reversing
research on netlist analysis research
and what he found was well a lot of the
stuff is not reproducible there are no
scripts for the algorithms given there's
no good
evaluation um or if there's something it
often immediately crashed when we uh put
our own net list in there so he sadly
had to conclude that research in this
area um has quite um has taken quite a
hit so what he wanted was an Ida Pro for
netlist reverse
engineering um so maybe like an open
framework with the ultimate goal to Aid
researchers and Professionals in their
everyday tasks so everyone should
benefit from
this um because this is hell but this is
Hell and Hell is our open source
framework as I said for netlist analysis
and it allows for automated and manual
and inspection of net lists of all kinds
so both A6 and of pgaas can be analyzed
here it's written in modern C++ 17 and
uh it offers support for custom plugins
so everyone can extend this framework
with his own ideas new
algorithms and so on and it also offers
a graphical user interface so what's the
idea behind hell well the main idea is
that we can represent a net list as a
graph as a multi-d graph to be specific
so a graph math graph Theory consists of
a set of vertices and edges and if you
think about it these edges that connect
vertices well this is just like Nets and
wires that connect net list elements so
actually it's like not difficult to map
a net list to such a graph structure and
this has the immediate benefit that we
can use the algorithms from graph Theory
and like they are well researched
there's a lot of thought in there and
this is also not something that we came
up with um graph representation is
basically the most common step in all of
the works on net list
analysis so how does Hell work well at
first you have to of course present it
with a net list and hell will pass this
net list into this graph
representation and then the user can
interact with this graph um either
through the graphical user interface or
via an included python shell but you can
also run hell as a standalone command
line tool for large scale
analysis but as I said you also have the
opportunity to load plugins and then uh
execute these plugins on the graph and
of course course all of this can
generate output you can get reports but
you can also modify the graph structure
and then write your modified net list
back out and since you might not work
alone on the project you can always
generate snapshots share them with other
researchers and they can continue or
join in on the work so let's first take
a look at hell and I will show you hell
later like in action but for the moment
let's just take a look at picture so I
can zoom in easily this is the main uh
view you get when you open hell
and let's focus on the left side first
so here the first thing you notice is
the graph View and I have opened a very
very small net list here and you can see
all the uh a few of the elements in
there and their
interconnections now let's suppose that
we want to get more information for
example on this element here so you
click on it and hell will give you a
detailed overview on what this actually
is and it displays all the associated
information so for example you can see
here that the type is a lot six so a
lookup table with six inputs you can see
the Boolean function that it implements
you can see the Nets that are connected
to inputs and output um and all kind of
associated information and this is also
true for all the other um kinds of
elements that you have in there so we
might also have noticed that there are
colors and these colors are not
meaningless um hell is made to help you
modularize your net list because if you
think of the image that I showed you
when I said what you think a net list
looks like you think that you have
separated modules that interact with
each other and this is also how you
write or design your Hardware in HDL but
after synthesis this is not visible
anymore so what like uh one of the
overarching goal of many reverse
engineering works is um we want to try
to recover some modularity back and so
hell allows you to create these modules
and you see in purple a module that has
been unfolded but in in green here a
module that has been folded and now if I
want to I can simply inspect this module
in isolation and the included parts so I
can get all the distracting stuff away
and focus on the part that I'm
interested in and to help you navigate
we added like um a tree structure of the
modules because they are hierarchical
and of course you can have multiple
views open on different um parts of the
net list on different isolations and you
can work your way around so on the right
side of the interface we have the python
environment and this is a super powerful
tool you have a python editor window
right on the top and Below you have a
console and they both interact directly
with the core of hell so with all the
included Gates and elements so you can
do an explorative analysis you don't
have to like close all the stuff think
about it write stuff down Implement a
new C++ plug-in you can do all of this
stuff live explorative in through this
python
interface and our vision for hell is
basically that you take your net list
you put it into hell you execute plugins
that you or others wrote and you invest
like your own critical
thinking and then you might actually get
from this mess of gates to some kind of
modular
representation and this is what we
designed the graphical user interface
for so to now actually take a look at
Hell uh I want to show you two examples
um where we used hell to actually um
improve the state of
research and the first example I want to
show you uh is a paper on the difficulty
of FSM based Hardware
fusc so what's
obfuscation imagine you have something
like this and you turn it into this this
is obious yeah you take something that
is comprehensible and turn it into
something that has the same
functionality but is way less
comprehensible um to put this like in
our in our big picture if we say that
the engineering way is easy very hand
wavy and the way back is not that easy
then by putting obfuscation into the
game we want to make the way back the
reverse engineering insanely difficult
without making the engineering any
worse and what we uh take a look at now
and what was analyzed in the paper are
finite State machines fsms and these are
your central control elements in digital
Hardware most of you have probably seen
a state machine but it basically works
like you have a set of states and upon
special events or conditions you
transition from your state to a
different state that controls other
parts think about like the ATM machine
that uh is in its state that it waits
for your cart and then transitions to
the next state where it waits for your
input or
something so in this paper among other
schemes the authors took a look at the
Haroon FSM obfuscation scheme and haon
um had the idea that we take the FSM the
original FSM in blue and we add dummy
States and dummy transitions uh in front
of these original FSM and they like they
point to each other there are a lot of
transitions that form Loops so if you do
not know the one perfect transition um
series to get you to the original
starting State you will be trapped in
this um dummy logic and also a reverse
engineer will be like uh massively held
back because he has to analyze all of
these dummy States and we will now take
a look at how we can reverse or break
Harpoon so there are basically three
steps the first step is we have to find
the obvious gated FSM because think
about it we have this massive sea of
gates and then as soon as we have found
the obvious gate at FSM the approach was
to recover the state transition graph so
what you just saw the circles with the
arrows and then maybe by just analyzing
the state transition graph we can
already break
Hao um
so let's talk about the first step how
do we find the obvious cated fsms well
State machines have a self-updating
structure because the next state always
depends on the current
state and the storage elements that
store the state they therefore influence
each other so every storage element has
an influence on all the other storage
elements if I were to Drew this in a
picture it would look like this you have
your state memory that has a feedback
loop through some transition logic which
may depend on external inputs and then
of course you have some output logic
that controls the rest of your circuit
and if you think about it from a math
point of view this looks like a strongly
connected component and this is a term
from graph Theory um which basically
says that from every element in this
component you can reach every other
element so a good idea might be to look
for these strongly connected components
and see what we find and then the next
step to recover the state transition
graph we have to take it all a look at
the candidates we have and we basically
we don't care about the output logic
yeah we don't care about what this
controls we want to get the state
transition graph so we also don't care
about the state memory instead we take
our state that we are looking at
currently so the initial State we can
get from reset behavior of the memory or
on fpga from an initialization vector
and then we brute force all the
remaining inputs and compute the
transition logic and this way we get all
the states that can be reached from our
current state and all these states we
put into our q and if we process the
queue to the end we will have all of the
states that are reachable by this um
finite State
machine so the final step is to analyze
the state transition graph and we will
now take a look at this how it looks in
hell
all right so I've uh prepared a small
net list here for you and um as you
might be able to see on the bottom it is
quite small it has 128 elements and if I
now go in there you can see that you
basically see nothing yeah you see a lot
of elements but you have no idea what
they mean how do they like interact how
can I work with this so I prepared a
short python script here and what this
basically does it groups all of the
input buffers and output buffers into
custom modules we don't want to look at
them and then it runs the strongly
connected component algorithm that we um
Supply from an external graph algorithm
plugin so if I run this code now you can
see that we get like a much more cleaned
up view on our net list you see here at
the top we have a module that uh has a
lot of outputs we have a module that has
a lot of inputs so these are input and
output buffers we are not interested in
them
and um here on the bottom we have like
two uh different modules we have a large
one let's let's look into this first and
we see like okay it's it's really large
it has a lot of elements and if you've
done Hardware design before you know
State machines are typically very small
as you can encode the states very
densely so let's go back and take a look
at the other module and this looks
actually kind of nice it looks very
small no um so let's first verify that
we might actually uh look at something
that is of Interest here so I will
select this flip-flop I have here and I
will isolate it in a new view so this is
just our flip-flop in isolation and I
can now use the arrow keys to navigate
to the output pin and follow basically
the output pin to everything that is
connected and in my list here I
immediately see a lookup table that is
also in the same module that is
candidate 2 here and if I follow this I
can immediately see like a small
feedback loop I see that my storage
element my flip-flop on the left reaches
the lookup table and the lookup table
has a feedback back to the logic element
so let's take a look at what this also
connects to in the same module and uh I
find two more flip uh two more um lookup
tables
here and if I see if I take a look now
at what these lookup tables connect to I
immediately find candidates that are in
the same module so the remaining
flip-flops and if I move this now
around we can see like a perfect
feedback structure for all of the
elements we have here so if I select all
the outgoing NS you see they for go back
to the uh to the storage elements and if
I select the elements in between you see
they all reach the logic um in between
so we actually have a strongly connected
component here now let me run the script
for the second part part the recovery of
the state transition graph and this is
actually the whole Brute Force code that
you see here and if I run
this we get this output and this is now
the state transition graph that was
recovered from just looking at the
transition logic and you can see here at
the top this is our initial State our
starting State we have like a lot of
transitions to other states that go back
and forth we have loops but then here we
have like a single transition and as
soon as we take this transition we never
go back to one of the prior States we
always stay below here so we can
directly conclude just from looking at
this that this upper part here will most
likely be the Haroon opio cated part and
this bottom part here is our original
FSM so with this short analysis We have
basically broken Haroon in this
example so
um just as a disclaimer at this point um
it's not that easy in reality um State
machines are like um
much not much more complex or bigger but
they are not easily found by just
looking for strongly connected
components but in the paper we have
described like a lot more uh techniques
and metrics how to find them better um
and yeah if if you're interested you are
welcome to read uh to look into our
research results so the second one I
want to show you and it's very short uh
is scan based reverse engineering and
this is research that was not done by us
but by uh researchers from the techon
University in hii in Israel and they
said okay these four steps of Asic
analysis to get to the net list so we
don't have a net list yet yeah these
four steps they are expensive they are
time consuming and you have to do a lot
of manual interaction so we don't want
to do that maybe we can find a different
path to get to a net l
and so they thought about scan
chains what is a scan chain well you
might think that your Hardware looks
like this that you have storage elements
logic and then storage elements again
but in reality almost all designs look
like
this or if I want to draw it a little
bit better like this all of your storage
elements basically form one or more
chains they are chained
together and depending on the the mode
you use them in they either just
transmit the data to the next storage
element the next flip-flop in the chain
or they just run their data through the
logic and compute
normally so why would anyone want to do
this well think about it you can take
your chip you can put a full internal
state in there by using the chain then
you can run it for for example one clock
cycle and then you can get the full
internal State out again so you have
cycle accurate Hardware debugging
basically this is perfect for testing
and this is why almost every chip has
one or more scan chains and they are
commonly or they should commonly be
disabled after testing but they aren't
always disabled and there's also work on
how to reenable the scan chains so how
can we reverse engineer using the scan
chain well the first challenge is we
have no idea how these flip flops are
connected through logic so what are the
dependencies between these flip flops
this is the first Challenge and uh the
researcher solved this by basically
putting in like an internal State and
then changing single bits and taking a
look in what changes in the output and
there are specialized algorithms to this
efficiently and this way we get
dependencies between the flip-flops so
now we know which flip flops are
connected through logic but we don't
know the logic yet and for this way they
take take like a specific State also
carefully crafted observe the output do
this again with a different state and so
on and if you do this with enough States
again there are algorithms that do this
efficiently you get the Boolean function
that is implemented by the
logic so the tool they developed uh the
the technique is called scandit and by
combining now an Asic that you can query
the scan chain on with a scan that tool
you basically get an approximation of
the net list so you do not get the
actual physical parts that are built in
there as you would get from opening it
up and looking at the layers but you get
an approximation that is correct to the
functional level and scan it was now or
is currently under development as a held
plug-in that is able to operate with
real Hardware with scan chain access but
also um to use a simulation of the
hardware and this is what we want to
brief look at
now so I also prepared a instance for
this and I have an empty net list here
if I want to enter this module it says
me this module is empty you can't enter
it and I prepared our scandid plug-in
with a simulation of a small addition
circuit so a multi-bit adder and the
first step I execute right now just
recover the dependencies between the the
storage elements the flip-flops so this
is what our recovered net list looks
like it's very small yeah but we
immediately see several flip-flops data
elements in here storage elements and
they are connected to lops logic blocks
as we call them and these logic blocks
they do not contain any function yet you
would uh make them out here in the
details so now let me run the second
part of the analysis this and this is
the part where we want to recover the
Boolean function and this is all done in
simulation right now and if I now click
again you can see um that there's like a
large Boolean function that is
implemented by this six input logic
block if I take a look at for example
another logic block you can see uh down
here there's another Boolean function so
this algorithm now recovered us a net
list of this Eda circuit that we can
work with that we can analyze but again
it's just an approximation it's not the
perfect net list that was um built in
the
Asic okay so I showed you around I
showed you basically um the internals
and the underlying principles of
Hardware design and Hardware reverse
engineering and I showed you where the
main problems are and the big problem
still is net list analysis net list
reverse engineering and
what we wanted or would like to see is
basically that you throw your net list
into hell and you're done but this is
not the case you just saw that in the uh
obio example um the reality looks like
this we take hell and we use it and it
helps us a lot but we always invest
manual thinking so reverse engineering
not only Hardware reverse engineering
reverse engineering in basically every
area always in involves human processes
and human thinking and this actually
sparked a completely new
interdisciplinary research Direction at
our University which we called cognitive
obfuscation and in this research we work
together with psychologists from our
University with a goal to involve the
human factors in research and
obfuscation because as you saw with the
um obvio
example it might have been difficult for
a machine to break
but for us as humans we are still like
our brain is still the best thing at
pattern matching and passing that we
have so just by looking at this we broke
it um and the idea here is to maybe get
some metrics that actually quantify the
real world ofation strength so strength
against human and machine and this is
then ultimately the goal that we might
be able to get novel techniques that are
strong against both parts so this is
ongoing research that was sparked uh in
part by uh Hell by our work on hell um
and that is currently being worked on
so for the
end I know I'm standing here and talking
to you but this was not my work um the
whole project has grown over the past
four years like not in a continuous
development but from time to time and
there's a team behind this that works uh
on hell and the core team are basically
Mark Sebastian and myself um Mark is not
actively working on Hell anymore as he
finished his PhD but Sebastian and
myself we are uh working on hell um disc
actively discussing the directions we
want to take um and we are coordinating
the rest of our team that consists of
several PhD students and student
assistants and I want to ask you for a
round of applause because without these
people this would not have been
possible
so while I'm thanking I also want to
thank these amazing people that created
the icons that you saw in this
presentation they never get thanked uh
enough and um yeah you can clap for
that and I want to end with a call we
need you because we want hell to grow
and we ourselves we can only work on
Hell uh in parttime because we are paid
to do research and sadly the research
Community does not see tool development
even if it is used for research as
research so you can help us with your
expertise in software design we are it
security researchers we are not software
Engineers so we can greatly benefit from
all the experience you have and any
contribution that you can make is
greatly appreciated because hell is open
source under MIT license on GitHub and
you can contact us through slack through
email or even through uh Twitter and and
uh yeah as I said we are greatly
thankful we appreciate all of your help
and with that I want to thank you for
your attention and take
questions thank you
Max uh if you would like to ask a
question please line up at the
microphones in the room um use the
chance to also ask questions why
Internet to the signal Angel uh signal
Angel do you have a question from the
net yes I have um are there any plans to
add a debugger or emulator to hell so um
I can watch Real World data um flow
through the
modules uh yes there actually are so
internally we are working on on a
simulator right now on a um on a cycle
accurate simulator at the moment um and
it works quite well um but it's not yet
in the state that we can release but um
still this is something that uh we
ourselves would really like to see in
hell you the idea of debugging this not
only from code but also visually so we
are definitely looking into that and we
want to implement this into hell
yes thank you microphone number four
your
question um I have a question about how
well this performs on larger circuits
like a modern fpga with hundreds of
thousands of Luts or you know an Asic
with billions of transistors um how how
well does does this perform yeah great
question um so hell as a uh as the tool
itself the hell core is perfectly fine
to handle even larger net lists um with
several hundred thousand Gates but the
graphical user interface um is not in a
sense as I said the vision that we have
for for hell with the user interface is
to support
modularization because even if you have
a net LST with 100K Gates looking at
those gates at the Sea of gates this
doesn't doesn't help you so what we
wanted to do is develop a graphical user
interface that supports this
modularization and this is what it is
made for so you can still run all your
large scale analysis um using the
command line version of Hell basically
and this is also what we did in our um
graph similarity paper that you can uh
find on the website of our
group but um for like visual inspection
of all of the gates in a large net list
hell is currently not the tool to
go mhone number one your
question um first question is it a
common thing to upate uh um finite State
machines in chips and uh it doesn't
change the function of the state machine
but is it somehow measurable uh if it
consumes more power or have the other
performance
metrics so um I think actually the next
talk will talk quite a bit about this so
I don't want to take uh too much out of
that but um like the answer is it it
depends yeah so there are a lot of works
on state machine obfuscation but in the
paper that I presented basically all of
them were broken all of the underlying
schemes so first take-home message from
my perspective they are not strong
second um you can from from my point of
view always find some Metric to
identify method X but the question is
does it work on method y it might be
that your obfuscation technique that you
think about results in a higher power
consumption but maybe the other
technique has all of the elements idle
but it has a lot of elements so like not
that high power consumption yeah so it's
a difficult question to answer that
broadly microphone number nine your
question oh hello hi how do you know how
thick the top layer of the Dy is before
removing it so
um if you think about it these um layers
if you could look inside um they are
clearly separated because you always
have your your your layer uh your metal
layer and the wires you have in there
then you have a few of interconnecting
VR and then uh wires again and this
cross-section view you can actually get
you can for example take your chip and
simply um not remove the top layer but
like rotate it and remove the entire
side and look at it or you can do this
via x-ray for example can get a
cross-section view of the
chip microphone number three your
question so um there's an old project
maybe 10 years old called
dgate are you uh how does that connect
to hell I see you already moving your
head yes um so dgate is a different um
oh let's say start uh is is applied to a
different point in the process dgate is
actually used to analyze the images that
you get the layer images and um reverse
engineer them so with dgate um the goal
is to get from the images to the net
list and maybe of course you can like
already incorporate some kind of
analysis in there but um the thing is
that this is not for
analyzing an existing net
list uh signal Angel do you have another
question from the net yes I do what do
you think about fpga protection with a
key such as a control lock to prevent
netlist reverse
engineering um interesting so there are
like so there there's one technique this
is bitstream encryption so of course
also with a key and um there have been
like several academic works that BAS
basically broke all available bitstream
encryption schemes um but also um from
what I recall the numbers of people that
actually use bitstream encryption is
very very small like in the single digit
percentage range um then there are of
course uh schemes that will also I think
be talked about in the next talk like
logic locking where you use a key to
basically um in you you change the
circuitry in a way that it only works
correct if you input the correct key and
with the wrong key it just works
incorrect it still works but it's
incorrect and this is a topic that is
like largely discussed and uh where like
several design flaws have already been
uncovered um so from my point of view
this is not a good thing but I think the
next talk will be like much more
detailed on
this uh microphone number three what is
your
question uh regarding the state machine
graph
uh
previously how do you conclude that the
upper part is the Harpoon part and the
lower part is the actual State machine
diagram um so I would just open it up
one more
time so this was the the graph that I
show and I know that this State up here
the 0000 State this is the initial State
and I know this by taking a look at um
the initialization values of these flip
flops this was an fpga net list and on
of on fpga you can initialize the flip
flop to a specific value on an ASC you
would have to look at what the reset
behavior of the flip-flop is and then
from this initial State I um Traverse
all these states and the idea behind
Haroon was to preent the original State
machine with like a net of states that
are interconnected and that have loops
but once you leave the Haroon part of
the state machine you never go back and
this is exactly what we see on this
transition between the state 110 and
001 once you have this transition you
never go back you always stay in this
lower part so this is where we concluded
that this lower part is the original
state machine because if you take a look
at the state before it goes back to the
0000 state so it should not um belong to
the haon uh to the original state
machine okay single Angel another
question please you use brute force to
explore a state machine um have you
tried machine learning like some of your
colleagues at bom to explore State
Machines of Internet
protocols
so the Brute Force approach that we took
was just to recover the um the Boolean
um the the state transitions of an
already discovered State machine
candidate so um we had to bruteforce all
the inputs that come from the remaining
circuitry and that not depend on the
state memory itself so machine learning
on that point does not help you at all
this is really just compute and take a
look at what comes out using uh machine
learning on the whole St on the whole
design on the Whole Net list to detect
State machines is a different top topic
this might be possible but think about
that you need for most of the machine
learning algorithms you need a lot of
training data and this is like really
difficult to get in Hardware design also
every uh synthesis suit um optimizes and
synthesizes differently so if you train
your um neural network with all the for
example netlist that you generated
yourself you will actually just learn
this one one
synthesizer from my point of view so I
don't think that machine learning is
applicable
here all right thank you uh signal Angel
one last question um how is debugging
done um when obfuscation is used what
tools do the people have that are
supposed to debug a
chip okay so I assume you you talk about
the designer now that obus skates his
own design and now wants to debug
well um it depends on the obus technique
used of course but as you saw in the
diagram the idea of ausc is that only
the the way back the reverse engineering
is hard and the forward Direction the
engineering part still say stays like
equivalently uh easy yeah engineering is
never easy um so there as as long as you
know how the obfuscation works and you
know because you used it you can always
in incorporate this in your tests there
are also works on this that say okay now
I have like a protected design I have a
design that is locked for example how
can I still apply testing data without
giving out the key to whatever entity
performs testing because this is also
often outsourced so there are works on
this um but it highly depends on what
you actually
use all right thank you Max for your
talk and for answering all the
questions